Friday, April 7, 2017

TPS65217 : The power management chip on BBB

TPS65217 is mounted in its C revision on BeagleBlone Black rev C and BeagleCore. This chip is in charge of power up/ power down and handles the voltages needed by the board.
For this note, we will ignore the push button action on the chip as we are not using it.

 

Features

TPS65217 provides:
  • 3 step down converters (up to 1,2A output each)
  • 2 LDOs (+ 2 load switches configurable as LDOs): 1&2: 100mA, 3&4: 400 mA (rev C)
  • 1 linear battery charger
  • White LEDs driver
  • Power path
It can be configured through its i²C interface:
  • all rails, power swtches, LDOs can be enabled/disabled
  • power up/down sequences can be programmed (non-persistent, must be programmed from chip startup)
  • over temperature limits

Power up/down sequence

Power up

The default power up sequence can work with any type of application. It is defined by strobes and delay times. On each strobe (from 1 to 7) the rail that is attached to the strobe is powered up. After a delay (from 1 to 10 ms), the next strobe occurs and so on. Several rails can be attached to the same strobe but a rail can be attached to 1 strobe only.
The power up sequence occurs when any power source is ON (USB/AC adaptor) and PWR_EN pin is asserted.

Power down

It follows the reverse power up sequence but with STROBE7 occuring first and continuing down to STROBE1.
If the application requires all strobes to occur at the same time (no delay), INSTDWN bit in SEQ6 shall be asserted.
The power down sequence occurs when any of the following events occurs:
  • SEQDWN bit is set
  • PWR_EN is pulled low
  • nRESET is pulled low
  • A fault occurs in the IC

Strobe 14/15

The strobes are not handled by the sequencer. They are used to control rails that are always ON and shall be powered up as soon as the device exits OFF state. The strobe can only be assigned for LDO1 and LDO2 rails.
For power down, the strobes occurs only if the OFF bit is set which means that they are still active in SLEEP mode.

 

Power good

These signals are here to indicate if an output is in regulation or at fault. They are monitored at all time and if a fault occurs, all output rails are powered down and the device enters OFF state.

Power path

The power path allows simultaneous and independend charging of the battery and powering of the system. The battery can be charged from USB or AC.
The power path prioritizes the AC over USB and both over battery input to power up the system.

 

Device functional modes

Mode Description
OFF PMIC is completely shut down with the exception of AC/USB monitoring inputs. To enter OFF state, OFF bit in STATUS register shall be asserted and then, PWR_EN pin whall go low. OFF state can only be enetered from ACTIVE state
ACTIVE All power rails are operational, and i²C is active.
SLEEP Low power mode. All power rails are turned OFF with the exception of LDO1 (but with a current of 1mA). To enter SLEEP state, OFF bit in STATUS register shall be de-asserted (0) and then, PWR_EN pin whall go low.
RESET All power rails are shut down and registers are reset. Stays in this state for 1 sec before returning to ACTIVE.


Block diagram


Power signals assignments on BBB (non-exhaustive)

Output Mapping Function
L1_VDCDC1 VDDS_DDR SDRAM
L2_VDCDC2 VDD_MPU
L3_VDCDC3 VDD_CORE
LS1_OUT VDD_1V8 SDRAM / MPU / ADC / USB / HDMI
LS2_OUT VDD_3V3A eMMC / EEPROM / USB / HDMI / LCD / nRESET / (BCM1 : Power Led) / HDMI / I2C0 (pull-up)
VLDO1 VIO / VRTC / VDD_S nRESET / Ext. Wakeup
VLDO2 VDD_3V3AUX Power Led
SYS1 & SYS2 SYS_5V User Leds / HDMI / USB
Moreover, the signal VDD_3V3B is created from SYS_5V and VDD_3V3A (Enable). It is used for : JTAG / UART0 / µSD / LAN / HDMI CEC.

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